Predicting Logic Synthesis Issues to Optimize Digital Design Iteration Time
June 4, 2024Qualcomm Engineering, 2023–24
Liaison(s): Gokce Sarar
Advisor(s): Matthew Spencer
Students(s): Diego Herrera Vicioso (TL-S), Noah Limpert (TL-F), Kaitlin Lucio, Ellie Sundheim (S), Alisha Chulani (F)
Logic synthesis, a step in the digital integrated circuit design process, consumes significant design time. Designers have to iterate several times with logic design tools to achieve the desired performance, and each iteration can take over a week. In collaboration with Qualcomm, a leading communications chip design innovator, the Qualcomm Clinic Team will leverage machine learning solutions to create a software tool that analyzes digital designs to help predict synthesis outcomes in a short time. The project aims to reduce total synthesis runs and improve design practices in the semiconductor industry by identifying design choices that may reduce the quality of synthesis results.